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? 2000 microchip technology inc. preliminary ds20070l-page 1 features ? single supply with operation down to 2.5v low power cmos technology - 1 ma active current typical -10 a standby current typical at 5.5v -5 a standby current typical at 3.0v organized as 8 blocks of 256 bytes (8 x 256 x 8) 2-wire serial interface bus, i 2 c ? compatible schmitt trigger inputs for noise suppression output slope control to eliminate ground bounce 100 khz (e-temp) and 400 khz (c/i-temp) compatibility self-timed write cycle (including auto-erase) page-write buffer for up to 16 bytes 2 ms typical write cycle time for page-write hardware write protect for entire memory can be operated as a serial rom factory programming (qtp) available esd protection > 4,000v 1,000,000 erase/write cycles guaranteed data retention > 200 years 8-pin dip, 8-lead soic, 8-lead tssop packages available for extended temperature ranges description the microchip technology inc. 24lc16b is a 16k bit electrically erasable prom. the device is organized as eight blocks of 256 x 8 bit memory with a 2-wire serial interface. low voltage design permits operation down to 2.5 volts with standby and active currents of only 5 a and 1 ma respectively. the 24lc16b also has a page-write capability for up to 16 bytes of data. the 24lc16b is available in the standard 8-pin dip surface mount soic and tssop packages. package types block diagram - commercial (c): 0c to +70c - industrial (i): -40c to +85c - automotive (e): -40c to +125c 24lc16b a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc wp scl sda 24lc16b a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc wp scl sda 8-lead pdip 8-lead soic 24lc16b a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc wp scl sda 8-lead tssop hv generator eeprom array page latches ydec xdec sense amp r/w control memory control logic i/o control logic wp sda scl v cc v ss i 2 c is a trademark of philips corporation. 24lc16b 16k 2.5v i 2 c? serial eeprom
24lc16b ds20070l-page 2 preliminary ? 2000 microchip technology inc. 1.0 electrical characteristics 1.1 maximum ratings* v cc ...................................................................................7.0v all inputs and outputs w.r.t. v ss ............... -0.3v to v cc +1.0v storage temperature ..................................... -65 c to +150 c ambient temp. with power applied ................-65 c to +125 c soldering temperature of leads (10 seconds) ............. +300 c esd protection on all pins .................................................. 4 kv *notice: stresses above those listed under ? maximum ratings ? may cause permanent damage to the device. this is a stress rat- ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: pin function table table 1-2: dc characteristics figure 1-1: bus timing start/stop name function v ss ground sda serial address/data i/o scl serial clock wp write protect input v cc +2.5v to 5.5v power supply a0, a1, a2 no internal connection vcc = +2.5v to +5.5v commercial (c): tamb = 0 c to +70 c industrial (i): tamb = -40 c to +85 c automotive (e) tamb = -40 c to +125 c parameter symbol min max units conditions wp, scl and sda pins: high level input voltage v ih .7 v cc ? v low level input voltage v il ? .3 v cc v hysteresis of schmitt trigger inputs v hys .05 v cc ? v (note) low level output voltage v ol ? .40 v i ol = 3.0 ma, v cc = 2.5v input leakage current i li -10 10 av in = .1v to v cc output leakage current i lo -10 10 ? v out = .1v to v cc pin capacitance (all inputs/outputs) c in , c out ? 10 pf v cc = 5.0v (note) ta m b = 2 5 c, f clk = 1mhz operating current i cc write i cc read ? ? 3 1 ma ma v cc = 5.5v, scl = 400 khz standby current i ccs ? ? 30 100 ? ? v cc = 3.0v, sda = scl = v cc v cc = 5.5v, sda = scl = v cc wp = v ss note: this parameter is periodically sampled and not 100% tested. t su : sta t hd : sta v hys t su : sto start stop scl sda
? 2000 microchip technology inc. preliminary ds20070l-page 3 24lc16b table 1-3: ac characteristics v cc = +2.5v to 5.5v commercial (c): tamb = 0 c to +70 c industrial (i): tamb = -40 c to +85 c automotive (e): tamb = -40 c to 125 c parameter symbol min max units conditions clock frequency fclk ? ? 400 100 khz 4.5v v cc 5.5v 2.5v v cc 5.5v (e-temp range) clock high time t high 600 4000 ? ? ns 4.5v v cc 5.5v 2.5v v cc 5.5v (e-temp range) clock low time t low 1300 4700 ? ? ns 4.5v v cc 5.5v 2.5v v cc 5.5v (e-temp range) sda and scl rise time (note 1) t r ? ? 300 1000 ns 4.5v v cc 5.5v ( note 1 ) 2.5v v cc 5.5v (e-temp range) ( note 1 ) sda and scl fall time t f ? 300 ns ( note 1 ) start condition hold time t hd : sta 600 4000 ? ? ns 4.5v vcc 5.5v 2.5v v cc 5.5v (e-temp range) start condition setup time t su : sta 600 4700 ? ? ns 4.5v vcc 5.5v 2.5v v cc 5.5v (e-temp range) data input hold time t hd : dat 0 ? ns ( note 2 ) data input setup time t su : dat 100 250 ? ? ns 4.5v vcc 5.5v 2.5v v cc 5.5v (e-temp range) stop condition setup time t su : sto 600 4000 ? ? ns 4.5v vcc 5.5v 2.5v v cc 5.5v (e-temp range) output valid from clock (note 2) t aa ? ? 900 3500 ns 4.5v vcc 5.5v 2.5v vcc 5.5v (e-temp range) bus free time: time the bus must be free before a new transmission can start t buf 1300 4700 ? ? ns 4.5v vcc 5.5v 2.5v v cc 5.5v (e-temp range) output fall time from v ih minimum to v il maximum t of 20+0.1c b ? 250 250 ns 4.5v v cc 5.5v 2.5v v cc 5.5v (e-temp range) input filter spike suppression (sda and scl pins) t sp ? 50 ns ( notes 1 and 3 ) write cycle time (byte or page) t wc ? 5ms endurance 1m ? cycles 25 c, vcc = 5.0v, block mode (note 4) note 1: not 100% tested. c b = total capacitance of one bus line in pf. note 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. note 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs which provide improved noise spike suppression. this eliminates the need for a ti specification for standard operation. note 4: this parameter is not tested but guaranteed by characterization. for endurance estimates in a specific application, please consult the total endurance model which can be obtained on microchip ? s website.
24lc16b ds20070l-page 4 preliminary ? 2000 microchip technology inc. figure 1-2: bus timing data t su : sta t f t low t high t r t hd : dat t su : dat t su : sto t hd : sta t buf t aa t aa t sp t hd : sta scl scl in scl out
? 2000 microchip technology inc. preliminary ds20070l-page 5 24lc16b 2.0 functional description the 24lc16b supports a bi-directional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access, and generates the start and stop conditions, while the 24lc16b works as slave. both, master and slave can operate as transmitter or receiver but the master device deter- mines which mode is activated. 3.0 bus characteristics the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 3-1). 3.1 bus not busy (a) both data and clock lines remain high. 3.2 start data transfer (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 3.3 stop data transfer (c) a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 3.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited, although only the last six- teen will be stored when doing a write operation. when an overwrite does occur it will replace data in a first in first out fashion. 3.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges, has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (24lc16b) will leave the data line high to enable the master to generate the stop con- dition. figure 3-1: data transfer sequence on the serial bus note: the 24lc16b does not generate any acknowledge bits if an internal program- ming cycle is in progress. scl sda (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition
24lc16b ds20070l-page 6 preliminary ? 2000 microchip technology inc. 3.6 device addressing a control byte is the first byte received following the start condition from the master device. the control byte consists of a four bit control code, for the 24lc16b this is set as 1010 binary for read and write operations. the next three bits of the control byte are the block select bits (b2, b1, b0). they are used by the master device to select which of the eight 256 word blocks of memory are to be accessed. these bits are in effect the three most significant bits of the word address. it should be noted that the protocol limits the size of the memory to eight blocks of 256 words, therefore the protocol can support only one 24lc16b per system. the last bit of the control byte defines the operation to be performed. when set to one a read operation is selected, when set to zero a write operation is selected. following the start condition, the 24lc16b monitors the sda bus checking the device type identifier being transmitted, upon a 1010 code the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the 24lc16b will select a read or write operation. figure 3-2: control byte allocation operation control code block select r/w read 1010 block address 1 write 1010 block address 0 x = don ? t care 1010b2b1b0 r/w a start read/write slave address
? 2000 microchip technology inc. preliminary ds20070l-page 7 24lc16b 4.0 write operation 4.1 byte write following the start condition from the master, the device code (4 bits), the block address (3 bits), and the r/w bit which is a logic low is placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the 24lc16b. after receiv- ing another acknowledge signal from the 24lc16b the master device will transmit the data word to be written into the addressed memory location. the 24lc16b acknowledges again and the master generates a stop condition. this initiates the internal write cycle, and during this time the 24lc16b will not generate acknowledge signals (figure 4-1). 4.2 page write the write control byte, word address and the first data byte are transmitted to the 24lc16b in the same way as in a byte write. but instead of generating a stop con- dition the master transmits up to 16 data bytes to the 24lc16b which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. after the receipt of each word, the four lower order address pointer bits are internally incremented by one. the higher order seven bits of the word address remains constant. if the master should transmit more than 16 words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received an inter- nal write cycle will begin (figure 4-2). figure 4-1: byte write figure 4-2: page write note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multi- ples of the page buffer size (or ? page size ? ) and end at addresses that are integer mul- tiples of [page size - 1]. if a page write com- mand attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the cur- rent page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page bound- ary. s p bus activity master sda line bus activity s t a r t s t o p control byte word address data a c k a c k a c k s p bus activity master sda line bus activity s t a r t control byte word address (n) data n data n + 15 s t o p a c k a c k a c k a c k a c k data n + 1
24lc16b ds20070l-page 8 preliminary ? 2000 microchip technology inc. 5.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master send- ing a start condition followed by the control byte for a write command (r/w = 0). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 5-1 for flow diagram. figure 5-1: acknowledge polling flow 6.0 write protection the 24lc16b can be used as a serial rom when the wp pin is connected to v cc . programming will be inhib- ited and the entire memory will be write-protected. 7.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read, and sequential read. 7.1 current address read the 24lc16b contains an address counter that main- tains the address of the last word accessed, internally incremented by one. therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with r/w bit set to one, the 24lc16b issues an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does gen- erate a stop condition and the 24lc16b discontinues transmission (figure 7-1). 7.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the 24lc16b as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then the master issues the control byte again but with the r/w bit set to a one. the 24lc16b will then issue an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24lc16b dis- continues transmission (figure 7-2). 7.3 sequential read sequential reads are initiated in the same way as a ran- dom read except that after the 24lc16b transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the 24lc16b to transmit the next sequentially addressed 8-bit word (figure 7-3). to provide sequential reads the 24lc16b contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. 7.4 noise protection the 24lc16b employs a v cc threshold detector circuit which disables the internal erase/write logic if the v cc is below 1.5 volts at nominal conditions. the scl and sda inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes
? 2000 microchip technology inc. preliminary ds20070l-page 9 24lc16b figure 7-1: current address read figure 7-2: random read figure 7-3: sequential read 8.0 pin descriptions 8.1 sda serial address/data input/output this is a bi-directional pin used to transfer addresses and data into and data out of the device. it is an open drain terminal, therefore the sda bus requires a pullup resistor to v cc (typical 10k ? for 100 khz, 2 k ? for 400 khz). for normal data transfer sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop condi- tions. 8.2 scl serial clock this input is used to synchronize the data transfer from and to the device. 8.3 wp this pin must be connected to either v ss or v cc . if tied to vss normal memory operation is enabled (read/write the entire memory 000-7ff). if tied to v cc , write operations are inhibited. the entire memory will be write-protected. read operations are not affected. this feature allows the user to use the 24lc16b as a serial rom when wp is enabled (tied to v cc ). 8.4 a0, a1, a2 these pins are not used by the 24lc16b. they may be left floating or tied to either v ss or v cc . sp bus activity master sda line bus activity s t a r t s t o p control byte data n a c k n o a c k s p s bus activity master sda line bus activity s t a r t s t o p control byte a c k word address (n) control byte s t a r t data (n) a c k a c k n o a c k p bus activity master sda line bus activity s t o p control byte a c k n o a c k data n data n + 1 data n + 2 data n + x a c k a c k a c k
24lc16b ds20070l-page 10 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds20070l-page 11 24lc16b 24lc16b product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. sales and support 24lc16b - t /p package: p = plastic dip (300 mil body) 8-lead sn = plastic soic (150 mil body),8-lead st = plastic tssop, 8-lead temperature blank = 0 c to +70 c range: i= ? 40 c to +85 c e= ? 40 c to +125 c device: 24lc16b = 16k i 2 c serial eeprom 24lc16bt = 16k i 2 c serial eeprom (tape and reel) data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 786-7277. 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
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